Invention Grant
- Patent Title: Chip package structure and chip packaging method
- Patent Title (中): 芯片封装结构和芯片封装方法
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Application No.: US13166998Application Date: 2011-06-23
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Publication No.: US08652882B2Publication Date: 2014-02-18
- Inventor: Yu Tang Pan , Shih Wen Chou
- Applicant: Yu Tang Pan , Shih Wen Chou
- Applicant Address: TW Hsinchu
- Assignee: Chipmos Technologies Inc.
- Current Assignee: Chipmos Technologies Inc.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, P.C.
- Agent Anthony King; Kay Yang
- Priority: TW099135167 20101015
- Main IPC: H01L23/44
- IPC: H01L23/44 ; H01L23/48

Abstract:
A chip packaging method includes the steps of: attaching a first tape to a metal plate; patterning the metal plate to form a plurality of terminal pads and a plurality of leads, wherein the plurality of terminal pads and the plurality of leads are disposed on two opposite sides of a central void region, the plurality of terminal pads on each side are arranged in at least two rows spaced apart from each other in the direction away from the central void region, and each lead has a first end portion extending to the central void region and a second end portion connecting to a corresponding terminal pad; attaching a second tape having openings to the plurality of terminal pads, wherein each of the openings exposes the central void region and the first end portions of the leads; removing the first tape; attaching a chip to the plurality of terminal pads and the plurality of leads, wherein a plurality of bond pads on the chip are corresponding to the central void region; and connecting the bond pads to the first end portions of the leads with a plurality of bonding wires through the opening.
Public/Granted literature
- US20120091570A1 CHIP PACKAGE STRUCTURE AND CHIP PACKAGING METHOD Public/Granted day:2012-04-19
Information query
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