Provided is a manufacturing method of semiconductor integrated circuit, which is effective when applied to a processing technique for a gate electrode or the like. In the patterning of a gate stack film having a high-k gate insulating film and a metal electrode film in a memory region, etching for a cut region between adjacent gate electrodes is performed first using a first resist film and, after the first resist film that is no longer needed is removed, etching for a line and space pattern is performed using a second resist film.