Invention Grant
- Patent Title: Dual vertical channel transistor and fabrication method thereof
- Patent Title (中): 双垂直沟道晶体管及其制造方法
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Application No.: US12727265Application Date: 2010-03-19
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Publication No.: US08653584B2Publication Date: 2014-02-18
- Inventor: Shing-Hwa Renn
- Applicant: Shing-Hwa Renn
- Applicant Address: TW Kueishan, Tao-Yuan Hsien
- Assignee: Nanya Technology Corp.
- Current Assignee: Nanya Technology Corp.
- Current Assignee Address: TW Kueishan, Tao-Yuan Hsien
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L29/78
- IPC: H01L29/78
Abstract:
A dual vertical channel transistor includes a tuning fork-shaped substrate body; a buried bit line embedded at a bottom of a recess between two prong portions of the tuning fork-shaped substrate body; an out-diffused drain region adjacent to the buried bit line in the tuning fork-shaped substrate body; a source region situated at a top portion of each of the two prong portions of the tuning fork-shaped substrate body; an epitaxial portion connecting the two prong portions of the tuning fork-shaped substrate body between the out-diffused drain region and the source region; a front gate situated on a first side surface of the tuning fork-shaped substrate body; and a back gate situated on a second side surface opposite to the first side surface of the tuning fork-shaped substrate body.
Public/Granted literature
- US20110227145A1 DUAL VERTICAL CHANNEL TRANSISTOR AND FABRICATION METHOD THEREOF Public/Granted day:2011-09-22
Information query
IPC分类:
