Invention Grant
- Patent Title: Method for packaging semiconductors at a wafer level
- Patent Title (中): 在晶圆级封装半导体的方法
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Application No.: US13331408Application Date: 2011-12-20
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Publication No.: US08653673B2Publication Date: 2014-02-18
- Inventor: Robert B. Hallock , William J. Davis , Yiwen Zhang , Ward G. Fillmore , Susan C. Trulli , Jason G. Milne
- Applicant: Robert B. Hallock , William J. Davis , Yiwen Zhang , Ward G. Fillmore , Susan C. Trulli , Jason G. Milne
- Applicant Address: US MA Waltham
- Assignee: Raytheon Company
- Current Assignee: Raytheon Company
- Current Assignee Address: US MA Waltham
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices.
Public/Granted literature
- US20130154124A1 METHOD FOR PACKAGING SEMICONDUCTORS AT A WAFER LEVEL Public/Granted day:2013-06-20
Information query
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