Invention Grant
- Patent Title: Low-current logic-gate circuit
- Patent Title (中): 低电流逻辑门电路
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Application No.: US13321117Application Date: 2010-06-15
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Publication No.: US08653854B2Publication Date: 2014-02-18
- Inventor: Erwin Spits , Léon C. M. van den Oever
- Applicant: Erwin Spits , Léon C. M. van den Oever
- Applicant Address: DE Munich
- Assignee: EPCOS AG
- Current Assignee: EPCOS AG
- Current Assignee Address: DE Munich
- Agency: Slater & Matsil, L.L.P.
- Priority: EP09162990 20090617
- International Application: PCT/EP2010/058388 WO 20100615
- International Announcement: WO2010/146051 WO 20101223
- Main IPC: H03K19/094
- IPC: H03K19/094

Abstract:
A circuit includes E-mode transistors with gate-source junction, a D-mode transistor with gate-source junction. A component generates a voltage drop between the source of the D-mode transistor and the drain of an E mode transistor provided as a signal output. A connection is made between this drain of the E-mode transistor and the gate of the D-mode transistor, and a signal input at the gates of the E-mode transistors.
Public/Granted literature
- US20120112793A1 Low-Current Logic-Gate Circuit Public/Granted day:2012-05-10
Information query
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