Invention Grant
US08653926B2 Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements 有权
具有最小图案密度要求的半导体技术的感性和电容元件

  • Patent Title: Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements
  • Patent Title (中): 具有最小图案密度要求的半导体技术的感性和电容元件
  • Application No.: US10564582
    Application Date: 2004-07-15
  • Publication No.: US08653926B2
    Publication Date: 2014-02-18
  • Inventor: Celine Juliette DetcheverryWibo Daniel Van Noort
  • Applicant: Celine Juliette DetcheverryWibo Daniel Van Noort
  • Applicant Address: NL Eindhoven
  • Assignee: NXP B.V.
  • Current Assignee: NXP B.V.
  • Current Assignee Address: NL Eindhoven
  • Priority: EP03102261 20030723
  • International Application: PCT/IB2004/051234 WO 20040715
  • International Announcement: WO2005/008695 WO 20050127
  • Main IPC: H01F5/00
  • IPC: H01F5/00
Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements
Abstract:
The present invention provides a semiconductor device comprising a plurality of layers, the semiconductor device comprising:—a substrate having a first major surface,—an inductive element fabricated on the first major surface of the substrate, the inductive element comprising at least one conductive line, and—a plurality of tilling structures in at least one layer, wherein the plurality of tilling structures are electrically connected together and are arranged in a geometrical pattern so as to substantially inhibit an inducement of an image current in the tilling structures by a current in the inductive element. It is an advantage of the above semiconductor device that, by using such tilling structures, an inductive element with improved quality factor is obtained. The present invention also provides a method for providing an inductive element in a semiconductor device comprising a plurality of layers.
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