Invention Grant
US08654597B2 Defective memory cell address storage circuit and redundancy control circuit including the same
失效
存储单元地址存储电路不良，冗余控制电路包括相同的
- Patent Title: Defective memory cell address storage circuit and redundancy control circuit including the same
- Patent Title (中): 存储单元地址存储电路不良，冗余控制电路包括相同的
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Application No.: US13191935Application Date: 2011-07-27
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Publication No.: US08654597B2Publication Date: 2014-02-18
- Inventor: Yong-Ho Kong
- Applicant: Yong-Ho Kong
- Applicant Address: KR Gyeonggi-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2010-0128929 20101216
- Main IPC: G11C29/00
- IPC: G11C29/00
Abstract:
A fail address storage circuit includes a fail address storage unit configured to store a fail address and a discrimination information storage unit configured to store information indicating whether a value stored in the fail address storage unit is a row address or column address.
Public/Granted literature
- US20120155202A1 DEFECTIVE MEMORY CELL ADDRESS STORAGE CIRCUIT AND REDUNDANCY CONTROL CIRCUIT INCLUDING THE SAME Public/Granted day:2012-06-21
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