Invention Grant
- Patent Title: System for reducing power consumption in an electronic chip
- Patent Title (中): 降低电子芯片功耗的系统
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Application No.: US13340311Application Date: 2011-12-29
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Publication No.: US08656200B2Publication Date: 2014-02-18
- Inventor: Kum Cheong Adam Chan , Chi Hock Goh , Poh Boon Teo
- Applicant: Kum Cheong Adam Chan , Chi Hock Goh , Poh Boon Teo
- Applicant Address: US TX Houston
- Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee Address: US TX Houston
- Main IPC: G06F1/30
- IPC: G06F1/30 ; G06F1/32
Abstract:
A system for reducing power consumption in an electronic device comprising at least one electronic chip comprises a plurality of local access network (LAN) ports, a transceiver coupled between the LAN ports and the electronic chip, a PLA device, and a central processing unit (CPU). The CPU is configured to power off the electronic chip in response to a period of inactivity on the LAN ports and power on the electronic chip in response to a signal from the PLA device.
Public/Granted literature
- US20120096296A1 SYSTEM FOR REDUCING POWER CONSUMPTION IN AN ELECTRONIC CHIP Public/Granted day:2012-04-19
Information query
