Invention Grant
- Patent Title: System and method for implementing power integrity topology adapted for parametrically integrated environment
- Patent Title (中): 适用于参数集成环境的电源完整性拓扑的系统和方法
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Application No.: US12979137Application Date: 2010-12-27
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Publication No.: US08656329B1Publication Date: 2014-02-18
- Inventor: Taranjit Singh Kukal , Feras Al-Hawari , Dennis Nagle , Raymond Komow , Jilin Tan
- Applicant: Taranjit Singh Kukal , Feras Al-Hawari , Dennis Nagle , Raymond Komow , Jilin Tan
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Rosenberg, Klein & Lee
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A system and method are provided for generating a programmably implemented model which emulates a power delivery network serving an integrated circuit (IC) core in an electronic system. The system and method generally comprise measures for establishing a power integrity (PI) topology including models for a voltage regulator module that generates at least one predetermined supply voltage level, and for a conductive power rail portion of the power delivery network (PDN). The system and method further comprise measures for interconnecting to the conductive power rail portion model a first behavioral model indicative of the current consumption characteristics of the IC core, and a second behavioral model indicative of the current consumption of an IO interface buffer driving an output signal of the electronic system.
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