A method, device, and article for assisting in the design of a logic circuit. The method can be such that: logic circuit description data is acquired, a first netlist is generated which is logically integrated with a first frequency based on the acquired logic circuit description data, and a second netlist is generated which is logically integrated with a second frequency higher than the first frequency based on the acquired logic circuit description data, logical operation elements and the wiring for the logical operation elements are arranged based on the first netlist, and a timing report is outputted which is related to the execution timing for each block divided into a predetermined wiring unit, and any block not satisfying the desired operational speed based on the outputted timing report is extracted, the first netlist is replaced with the second netlist for any extracted block, and placement and routing is performed.