Invention Grant
- Patent Title: Method for reducing loadline impedance in a system
- Patent Title (中): 减少系统中负载线阻抗的方法
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Application No.: US11588682Application Date: 2006-10-27
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Publication No.: US08659909B2Publication Date: 2014-02-25
- Inventor: Damion Searls , Edward Osburn
- Applicant: Damion Searls , Edward Osburn
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: H05K7/02
- IPC: H05K7/02 ; H05K7/06 ; H05K7/08 ; H05K7/10
Abstract:
In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.
Public/Granted literature
- US20070074389A1 Reducing loadline impedance in a system Public/Granted day:2007-04-05
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