Invention Grant
US08660234B2 RAM based implementation for scalable, reliable high speed event counters
失效
基于RAM的实现可扩展,可靠的高速事件计数器
- Patent Title: RAM based implementation for scalable, reliable high speed event counters
- Patent Title (中): 基于RAM的实现可扩展,可靠的高速事件计数器
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Application No.: US12183748Application Date: 2008-07-31
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Publication No.: US08660234B2Publication Date: 2014-02-25
- Inventor: Carl Alfred Bender , Peter Heiner Hochschild , Ashutosh Misra , Richard Swetz
- Applicant: Carl Alfred Bender , Peter Heiner Hochschild , Ashutosh Misra , Richard Swetz
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Roy W. Truelson
- Main IPC: H03K21/00
- IPC: H03K21/00

Abstract:
There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated “pre-counter” while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the “sweeper” state machine accesses the pre-counter.
Public/Granted literature
- US20100027735A1 RAM BASED IMPLEMENTATION FOR SCALABLE, RELIABLE HIGH SPEED EVENT COUNTERS Public/Granted day:2010-02-04
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