Invention Grant
- Patent Title: Error detection and correction scheme for a memory device
- Patent Title (中): 存储器件的错误检测和校正方案
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Application No.: US13080299Application Date: 2011-04-05
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Publication No.: US08661312B2Publication Date: 2014-02-25
- Inventor: William H. Radke , Shuba Swaminathan , Brady L. Keays
- Applicant: William H. Radke , Shuba Swaminathan , Brady L. Keays
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Leffert Jay & Polglaze, P.A.
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller circuit. If an error is present that can be corrected by the Hamming code correction operation, this is performed and the Reed-Solomon code detection operation is performed on the corrected word. If the error is uncorrectable by the Hamming code, the Reed-Solomon code correction operation is performed on the word.
Public/Granted literature
- US20110185254A1 ERROR DETECTION AND CORRECTION SCHEME FOR A MEMORY DEVICE Public/Granted day:2011-07-28
Information query
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