Invention Grant
- Patent Title: Multiple mold structure methods of manufacturing vertical memory devices
- Patent Title (中): 制造垂直存储器件的多种模具结构方法
-
Application No.: US13596621Application Date: 2012-08-28
-
Publication No.: US08664101B2Publication Date: 2014-03-04
- Inventor: Hyo-Jung Kim , Dae-Hong Eom , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Kyung-Hyun Kim
- Applicant: Hyo-Jung Kim , Dae-Hong Eom , Jong-Heun Lim , Myung-Jung Pyo , Byoung-Moon Yoon , Kyung-Hyun Kim
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Priority: KR10-2011-0091289 20110908
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/4763

Abstract:
A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.
Public/Granted literature
- US20130065386A1 MULTIPLE MOLD STRUCTURE METHODS OF MANUFACTURING VERTICAL MEMORY DEVICES Public/Granted day:2013-03-14
Information query
IPC分类: