Invention Grant
- Patent Title: Wiring substrate and manufacturing method thereof
- Patent Title (中): 接线基板及其制造方法
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Application No.: US13153590Application Date: 2011-06-06
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Publication No.: US08664536B2Publication Date: 2014-03-04
- Inventor: Masahiro Sunohara , Shigeaki Suganuma
- Applicant: Masahiro Sunohara , Shigeaki Suganuma
- Applicant Address: JP Nagano-Shi
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano-Shi
- Agency: Kratz, Quintos & Hanson, LLP
- Priority: JP2010-130422 20100607
- Main IPC: H05K1/09
- IPC: H05K1/09

Abstract:
A wiring substrate includes a wiring layer made of copper, an electrode layer made of copper, and an insulating layer arranged adjacent to the electrode layer. The wiring layer is stacked on the electrode layer and the insulating layer. The insulating layer and the wiring layer are stacked with an adhesive layer interposed between the insulating layer and the wiring layer. The electrode layer and the wiring layer are stacked with a copper alloy layer formed adjacent to the adhesive layer and interposed between the electrode layer and the wiring layer.
Public/Granted literature
- US20110297426A1 WIRING SUBSTRATE AND MANUFACTURING METHOD THEREOF Public/Granted day:2011-12-08
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