Invention Grant
US08664721B2 FET with FUSI gate and reduced source/drain contact resistance
有权
具有FUSI栅极的FET和降低的源极/漏极接触电阻
- Patent Title: FET with FUSI gate and reduced source/drain contact resistance
- Patent Title (中): 具有FUSI栅极的FET和降低的源极/漏极接触电阻
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Application No.: US13569741Application Date: 2012-08-08
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Publication No.: US08664721B2Publication Date: 2014-03-04
- Inventor: Christian Lavoie , Tak H. Ning , Qiqing Ouyang , Paul Solomon , Zhen Zhang
- Applicant: Christian Lavoie , Tak H. Ning , Qiqing Ouyang , Paul Solomon , Zhen Zhang
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Louis Percello
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/45
Abstract:
A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.
Public/Granted literature
- US20120299102A1 FET with FUSI Gate and Reduced Source/Drain Contact Resistance Public/Granted day:2012-11-29
Information query
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