Invention Grant
- Patent Title: Routing layer for mitigating stress in a semiconductor die
- Patent Title (中): 用于减轻半导体管芯中的应力的路由层
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Application No.: US13647052Application Date: 2012-10-08
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Publication No.: US08664777B2Publication Date: 2014-03-04
- Inventor: Roden Topacio , Gabriel Wong
- Applicant: ATI Technologies ULC
- Applicant Address: CA Markham, Ontario
- Assignee: ATI Technologies ULC
- Current Assignee: ATI Technologies ULC
- Current Assignee Address: CA Markham, Ontario
- Agency: Faegre Baker Daniels LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.
Public/Granted literature
- US20130032941A1 ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE Public/Granted day:2013-02-07
Information query
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