Invention Grant
- Patent Title: System to generate a predetermined fractional period time delay
- Patent Title (中): 系统以产生预定的分数周期时间延迟
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Application No.: US13790002Application Date: 2013-03-08
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Publication No.: US08664994B1Publication Date: 2014-03-04
- Inventor: Bharadwaj Amrutur , Pratap Kumar Das
- Applicant: Department of Electronics and Information Technology , Indian Institute of Science
- Applicant Address: IN New Delhi IN Bangalore
- Assignee: Department of Electronics and Information Technology,Indian Institute of Science
- Current Assignee: Department of Electronics and Information Technology,Indian Institute of Science
- Current Assignee Address: IN New Delhi IN Bangalore
- Agency: The Webb Law Firm
- Priority: IN4212/CHE/2012 20121010
- Main IPC: H03H11/26
- IPC: H03H11/26

Abstract:
Embodiments of the disclosure relate to an all-digital technique for generating an accurate delay irrespective of the inaccuracies of a controllable delay line. A sub-sampling technique based delay measurement unit capable of measuring delays accurately for the full period range is used as the feedback element to build accurate fractional period delays based on input digital control bits. The delay generation system periodically measures and corrects the error and maintains it at the minimum value without requiring any special calibration phase. A significant improvement in accuracy is obtained for a commercial programmable delay generator chip. The time-precision trade-off feature of the delay measurement unit is utilized to reduce the locking time. Loop dynamics are adjusted to stabilize the delay after the minimum error is achieved, thus avoiding additional jitter.
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