A harmonic input current reduction and power factor correction circuit for three phase, power supplies. The circuit includes passive elements including a series inductance and capacitor connected between each AC line of a three phase voltage source, and each input phase of the uncorrected power supply. The inductance and capacitor are designed and chosen to meet linearity and volt ampere requirements to achieve total harmonic current levels of less than 10%, and power factors greater than 0.98. This is achieved with less than 1% loss in line operating input voltage range and overall efficiency of greater than 99.5%. Further, the dynamic response of a circuit to power supply load transient demands is limited in voltage overshoot or undershoot effects.