Invention Grant
US08665661B2 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield
有权
半导体存储器件能够实现具有高操作可靠性和高产量的芯片
- Patent Title: Semiconductor memory device capable of realizing a chip with high operation reliability and high yield
- Patent Title (中): 半导体存储器件能够实现具有高操作可靠性和高产量的芯片
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Application No.: US13589523Application Date: 2012-08-20
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Publication No.: US08665661B2Publication Date: 2014-03-04
- Inventor: Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
- Applicant: Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
- Applicant Address: JP Kawasaki-shi
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Kawasaki-shi
- Agency: Banner & Witcoff, Ltd.
- Priority: JP10-187398 19980702
- Main IPC: G11C8/00
- IPC: G11C8/00

Abstract:
A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.
Public/Granted literature
- US20120314497A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REALIZING A CHIP WITH HIGH OPERATION RELIABILITY AND HIGH YIELD Public/Granted day:2012-12-13
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