Briefly stated, technologies are generally described for accessing a data block in a cache with a domain based cache coherence protocol. A first processor in a first tile and first domain can be configured to evaluate a request to access the data block. A cache in a second tile in the first domain can be configured to send the data block to the first tile when the data block is cached in the second tile. The first processor can be configured to send the request to a third tile in another domain when the cached location is outside the first processor's domain. The third processor can be configured to determine and send the request to a data domain associated with the cached location of the data block. A fourth tile can be configured to receive the request and send the data block to the first tile.