Invention Grant
- Patent Title: Error correction and recovery in chained memory architectures
- Patent Title (中): 链接内存架构中的纠错和恢复
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Application No.: US13757432Application Date: 2013-02-01
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Publication No.: US08667358B2Publication Date: 2014-03-04
- Inventor: David R. Resnick
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G06F11/00
- IPC: G06F11/00
Abstract:
Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data flow from two directions. The memory unit can be configured serially in a chain with other memory units. The chain can include an error check and correcting unit (ECC). Additional apparatus, systems, and methods are disclosed.
Public/Granted literature
- US20130145207A1 ERROR CORRECTION AND RECOVERY IN CHAINED MEMORY ARCHITECTURES Public/Granted day:2013-06-06
Information query
