Invention Grant
- Patent Title: Method of optimization of a manufacturing process of an integrated circuit layout
- Patent Title (中): 集成电路布局制造工艺优化方法
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Application No.: US13402941Application Date: 2012-02-23
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Publication No.: US08667427B2Publication Date: 2014-03-04
- Inventor: David L. DeMaris , Maria Gabrani , Ekaterina Volkova
- Applicant: David L. DeMaris , Maria Gabrani , Ekaterina Volkova
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Priority: EP11155878 20110224
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.
Public/Granted literature
- US20120221984A1 METHOD OF OPTIMIZATION OF A MANUFACTURING PROCESS OF AN INTEGRATED CIRCUIT LAYOUT Public/Granted day:2012-08-30
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