Invention Grant
US08667439B1 Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost
有权
将SoC IP内核自动连接到互连节点,以最大限度地减少全局延迟并降低互连成本
- Patent Title: Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost
- Patent Title (中): 将SoC IP内核自动连接到互连节点,以最大限度地减少全局延迟并降低互连成本
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Application No.: US13961809Application Date: 2013-08-07
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Publication No.: US08667439B1Publication Date: 2014-03-04
- Inventor: Sailesh Kumar , Eric Norige
- Applicant: NetSpeed Systems
- Applicant Address: US CA San Jose
- Assignee: NetSpeed Systems
- Current Assignee: NetSpeed Systems
- Current Assignee Address: US CA San Jose
- Agency: Procopio, Cory, Hargreaves & Savitch LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of various hosts in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example implementations selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, and using probabilistic functions to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.
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