Invention Grant
US08667454B1 System, method, and computer program product for optimizing pins
有权
系统，方法和计算机程序产品，用于优化引脚
- Patent Title: System, method, and computer program product for optimizing pins
- Patent Title (中): 系统，方法和计算机程序产品，用于优化引脚
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Application No.: US13160992Application Date: 2011-06-15
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Publication No.: US08667454B1Publication Date: 2014-03-04
- Inventor: Narasimha Murthy Palla Subrahmanya , Srinivasa Ravi Vedula , Nishitkumar Manharbhai Patel , Nagesh C. Gupta
- Applicant: Narasimha Murthy Palla Subrahmanya , Srinivasa Ravi Vedula , Nishitkumar Manharbhai Patel , Nagesh C. Gupta
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Holland & Knight LLP
- Agent Mark H. Whittenberger, Esq.
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
The present disclosure relates to a computer-implemented method for synthesis of device I/O associated with a printed circuit board (PCB) design. The method may include generating a first programmable device model and a second device model. The method may further include determining one or more pin assignments associated with the first programmable device model and the second device model based upon, at least in part, one or more of a breakout pattern, a breakout location and a fanout location, the one or more pin assignments configured to minimize one or more crossovers.
Information query
