Invention Grant
- Patent Title: Non-volatile memory (NVM) and logic integration
- Patent Title (中): 非易失性存储器(NVM)和逻辑集成
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Application No.: US13780574Application Date: 2013-02-28
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Publication No.: US08669158B2Publication Date: 2014-03-11
- Inventor: Mark D. Hall , Frank K. Baker, Jr. , Mehul D. Shroff
- Applicant: Mark D. Hall , Frank K. Baker, Jr. , Mehul D. Shroff
- Agent Joanna G. Chiu; James L. Clingan, Jr.
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/66

Abstract:
A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer.
Public/Granted literature
- US20130178027A1 NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION Public/Granted day:2013-07-11
Information query
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