Invention Grant
- Patent Title: Method, system, and program product to implement detail routing for double pattern lithography
- Patent Title (中): 方法，系统和程序产品实现双模式光刻的细节布线
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Application No.: US12980744Application Date: 2010-12-29
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Publication No.: US08671368B1Publication Date: 2014-03-11
- Inventor: Jeffrey Scott Salowe , Satish Samuel Raj
- Applicant: Jeffrey Scott Salowe , Satish Samuel Raj
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design.
Information query
