Invention Grant
US08677172B2 Method and system for correcting error in a PLL generated clock signal using a system clock of lower frequency and/or accuracy
有权
使用较低频率和/或精度的系统时钟校正PLL生成的时钟信号中的误差的方法和系统
- Patent Title: Method and system for correcting error in a PLL generated clock signal using a system clock of lower frequency and/or accuracy
- Patent Title (中): 使用较低频率和/或精度的系统时钟校正PLL生成的时钟信号中的误差的方法和系统
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Application No.: US12989543Application Date: 2009-04-21
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Publication No.: US08677172B2Publication Date: 2014-03-18
- Inventor: Peter Anderson , Jacqueline Bickerstaff , Xianri Huang
- Applicant: Peter Anderson , Jacqueline Bickerstaff , Xianri Huang
- Applicant Address: unknown Plan-les-Ouates
- Assignee: ST-Ericsson SA
- Current Assignee: ST-Ericsson SA
- Current Assignee Address: unknown Plan-les-Ouates
- Agency: Coats & Bennett, P.L.L.C.
- Priority: GB0807625.9 20080425
- International Application: PCT/GB2009/001027 WO 20090421
- International Announcement: WO2009/130460 WO 20091029
- Main IPC: G06F1/04
- IPC: G06F1/04 ; G06F11/00

Abstract:
The present invention provides a system for detecting timing characteristics of internal signals in a communications device, the system comprising: a system clock running at a known frequency; a test counter having a test input at which an internal signal to be tested is received; a gating counter having an input arranged to receive the system clock signal; and a system controller for controlling the counters; wherein the system controller controls the gating counter to count a predetermined number of system clock cycles to define a test period, and during the test period the test counter counts the cycles of the internal signal under test, whereby timing characteristics of the internal signal may be found with reference to a time base defined by the system clock. An associated method of operation is also described.
Public/Granted literature
- US20110068828A1 Method and System for Detecting Timing Characteristics in a Communications System Public/Granted day:2011-03-24
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