Invention Grant
- Patent Title: Cable redundancy and failover for multi-lane PCI express IO interconnections
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Application No.: US12959981Application Date: 2010-12-03
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Publication No.: US08677176B2Publication Date: 2014-03-18
- Inventor: Patrick A. Buckland , Jay R. Herring , Gregory M. Nordstrom , William A. Thompson
- Applicant: Patrick A. Buckland , Jay R. Herring , Gregory M. Nordstrom , William A. Thompson
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Patterson & Sheridan, LLP
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device. In response to detecting the failure in the first link, at an IO device end, the first set of lanes is switched with the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes.
Public/Granted literature
- US20120144230A1 CABLE REDUNDANCY AND FAILOVER FOR MULTI-LANE PCI EXPRESS IO INTERCONNECTIONS Public/Granted day:2012-06-07
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