A computer system including a first processor, an error detecting circuit and a south bridge chip is provided. The first processor outputs a first catastrophic error signal. The error detecting circuit is coupled to the first processor to receive the first catastrophic error signal. When the first catastrophic error signal changes to a first level and is maintained for a period exceeding a first predetermined time, the error detecting circuit outputs an internal error reset signal. When the first catastrophic error signal changes to a first level and passes a second predetermined time, the error detecting circuit outputs a machine error reset signal. Here, the second predetermined time is greater than the first predetermined time. The south bridge chip is coupled to the error detecting circuit and reboots the computer system according the internal error reset signal or the machine error reset signal.