Invention Grant
- Patent Title: Method and system for error correction in flash memory
- Patent Title (中): 闪存中纠错方法和系统
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Application No.: US13926514Application Date: 2013-06-25
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Publication No.: US08677215B2Publication Date: 2014-03-18
- Inventor: Aditya Ramamoorthy , Zining Wu , Pantas Sutardja
- Applicant: Marvell World Trade Ltd.
- Applicant Address: BB St. Michael
- Assignee: Marvell World Trade Ltd.
- Current Assignee: Marvell World Trade Ltd.
- Current Assignee Address: BB St. Michael
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal.
Public/Granted literature
- US20130290813A1 Method and System For Error Correction in Flash Memory Public/Granted day:2013-10-31
Information query
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