Invention Grant
US08677219B2 Method and apparatus for adapting a bit interleaver to LDPC codes and modulations under AWGN channel conditions using binary erasure surrogate channels 失效
用于使用二进制擦除代理信道在AWGN信道条件下使比特交织器适应LDPC码和调制的方法和装置

  • Patent Title: Method and apparatus for adapting a bit interleaver to LDPC codes and modulations under AWGN channel conditions using binary erasure surrogate channels
  • Patent Title (中): 用于使用二进制擦除代理信道在AWGN信道条件下使比特交织器适应LDPC码和调制的方法和装置
  • Application No.: US12998270
    Application Date: 2009-10-02
  • Publication No.: US08677219B2
    Publication Date: 2014-03-18
  • Inventor: Jing LeiWen Gao
  • Applicant: Jing LeiWen Gao
  • Applicant Address: FR Boulogne-Billancourt
  • Assignee: Thomson Licensing
  • Current Assignee: Thomson Licensing
  • Current Assignee Address: FR Boulogne-Billancourt
  • Agent Robert D. Shedd; Jeffrey M. Navon
  • International Application: PCT/US2009/005437 WO 20091002
  • International Announcement: WO2010/039257 WO 20100408
  • Main IPC: H03M13/00
  • IPC: H03M13/00
Method and apparatus for adapting a bit interleaver to LDPC codes and modulations under AWGN channel conditions using binary erasure surrogate channels
Abstract:
The present invention relates to code-dependent bit interleavers for parallel non-uniform channels. Since the channel dependence of a given code ensemble is dominated by the mutual information between the channel input and output, the present invention proposes to simplify the analysis about the decoding behavior by using a set of surrogate binary erasure channels. The approximation of the actual channel by the surrogate BEC is established on the equivalence of bitwise capacities, which represent the mutual information between the uniformly-distributed binary input and the likelihood ratios of the effective parallel AWGN channels. Moreover, the transition of the erasure probabilities is modeled by a linear difference equation around the decoding threshold SNR, from which we can derive a necessary condition on the convergence of decoding iterations and achieve a useful guideline for the configuration of the bit interleaver.
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