Invention Grant
- Patent Title: Semiconductor memory device
- Patent Title (中): 半导体存储器件
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Application No.: US13709995Application Date: 2012-12-10
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Publication No.: US08681565B2Publication Date: 2014-03-25
- Inventor: Takanori Ueda , Masayoshi Nakayama , Kazuyuki Kouno
- Applicant: Panasonic Corporation
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2010-131801 20100609
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
A main bit line is disposed between a reference main bit line and core main bit lines. A selection transistor disposed between a sub bit line connected to a cell and the main bit line can switch between a conductive state and a non-conductive state independently of other selection transistors. A dummy main bit line can be set to ground potential by a shield grounding section, and can be used as a shield line of the reference main bit line.
Public/Granted literature
- US20130148423A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2013-06-13
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