Invention Grant
US08683181B2 Processor and method for distributing load among plural pipeline units
失效
用于在多个流水线单元之间分配负载的处理器和方法
- Patent Title: Processor and method for distributing load among plural pipeline units
- Patent Title (中): 用于在多个流水线单元之间分配负载的处理器和方法
-
Application No.: US12926799Application Date: 2010-12-09
-
Publication No.: US08683181B2Publication Date: 2014-03-25
- Inventor: Hideki Okawara
- Applicant: Hideki Okawara
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Staas & Halsey LLP
- Priority: JP2009-294196 20091225
- Main IPC: G06F9/30
- IPC: G06F9/30
Abstract:
An arithmetic processor includes a first pipeline unit configured to execute a first instruction that is input; a second pipeline unit configured to execute a second instruction that is input; a registration unit into which an aborted instruction is registered, the aborted instruction being the first instruction when the first pipeline unit is unable to complete the first instruction or the second instruction when the second pipeline unit is unable to complete the second instruction; a determination unit configured to make a determination as to which one of the first pipeline unit and the second pipeline unit is operating under a lower load; and an input unit configured to input, in the first pipeline unit or the second pipeline unit that is determined as operating under the lower load by the determination unit, the aborted instruction that is registered in the registration unit.
Public/Granted literature
- US20110161629A1 Arithmetic processor, information processor, and pipeline control method of arithmetic processor Public/Granted day:2011-06-30
Information query
