Invention Grant
- Patent Title: Parallel packetized interconnect with simplified data link layer
- Patent Title (中): 具有简化数据链路层的并行分组互连
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Application No.: US12980602Application Date: 2010-12-29
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Publication No.: US08683285B2Publication Date: 2014-03-25
- Inventor: Jack Regula
- Applicant: Jack Regula
- Applicant Address: US CA Sunnyvale
- Assignee: PLX Technology, Inc.
- Current Assignee: PLX Technology, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Beyer Law Group LLP
- Main IPC: G08C25/02
- IPC: G08C25/02 ; H04L1/18

Abstract:
In a first embodiment of the present invention, a method for error-correcting in a parallel interconnect transmitting device is provided, the method comprising: detecting a frame transition in a transmission from the transmitting device to a parallel interconnect receiving device; tracking time between the frame transition and a transition of a response signal corresponding to the frame transition received from the receiving device; detecting an error in the transmission; and restarting a portion of the transmission in response to the error, wherein the size of the portion of the transmission to restart is based upon the tracked time between the frame transition and the transition of a response signal corresponding to the frame transition.
Public/Granted literature
- US20120173945A1 PARALLEL PACKETIZED INTERCONNECT WITH SIMPLIFIED DATA LINK LAYER Public/Granted day:2012-07-05
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