Invention Grant
- Patent Title: Chip assembly having via interconnects joined by plating
-
Application No.: US12883421Application Date: 2010-09-16
-
Publication No.: US08685793B2Publication Date: 2014-04-01
- Inventor: Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia
- Applicant: Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L23/522
- IPC: H01L23/522

Abstract:
An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element.
Public/Granted literature
- US20120068351A1 CHIP ASSEMBLY HAVING VIA INTERCONNECTS JOINED BY PLATING Public/Granted day:2012-03-22
Information query
IPC分类: