Invention Grant
- Patent Title: Memory device and method for manufacturing the same
- Patent Title (中): 存储器件及其制造方法
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Application No.: US13052426Application Date: 2011-03-21
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Publication No.: US08686384B2Publication Date: 2014-04-01
- Inventor: Kenji A{dot over (o)}yama , Kazuhiko Yamamoto , Satoshi Ishikawa , Shigeto Oshino
- Applicant: Kenji A{dot over (o)}yama , Kazuhiko Yamamoto , Satoshi Ishikawa , Shigeto Oshino
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-246525 20101102
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.
Public/Granted literature
- US20120104352A1 MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2012-05-03
Information query
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