Invention Grant
US08686473B1 Apparatus and method for reducing the interface resistance in GaN heterojunction FETs
有权
用于降低GaN异质结FET中的界面电阻的装置和方法
- Patent Title: Apparatus and method for reducing the interface resistance in GaN heterojunction FETs
- Patent Title (中): 用于降低GaN异质结FET中的界面电阻的装置和方法
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Application No.: US12792529Application Date: 2010-06-02
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Publication No.: US08686473B1Publication Date: 2014-04-01
- Inventor: Miroslav Micovic , Andrea Corrion , Keisuke Shinohara , Peter J Willadsen , Shawn D Burnham , Hooman Kazemi , Paul B Hashimoto
- Applicant: Miroslav Micovic , Andrea Corrion , Keisuke Shinohara , Peter J Willadsen , Shawn D Burnham , Hooman Kazemi , Paul B Hashimoto
- Applicant Address: US CA Malibu
- Assignee: HRL Laboratories, LLC
- Current Assignee: HRL Laboratories, LLC
- Current Assignee Address: US CA Malibu
- Agent Daniel R. Allemeier; George R. Rapacki
- Main IPC: H01L29/15
- IPC: H01L29/15 ; H01L31/0256 ; H01L29/66 ; H01L31/102
Abstract:
The interface resistance between the source/drain and gate of an HFET may be significantly reduced by engineering the bandgap of the 2DEG outside a gate region such that the charge density is substantially increased. The resistance may be further reduced by using an n+GaN Cap layer over the channel layer and barrier layer such that a horizontal surface of the barrier layer beyond the gate region is covered by the n+GaN Cap layer. This technique is applicable to depletion and enhancement mode HFETs.
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