Invention Grant
- Patent Title: Source/drain extension control for advanced transistors
- Patent Title (中): 高级晶体管的源/漏扩展控制
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Application No.: US14030471Application Date: 2013-09-18
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Publication No.: US08686511B2Publication Date: 2014-04-01
- Inventor: Pushkar Ranade , Lucian Shifren , Sachin R. Sonkusale
- Applicant: SuVolta, Inc.
- Applicant Address: US CA Los Gatos
- Assignee: SuVolta, Inc.
- Current Assignee: SuVolta, Inc.
- Current Assignee Address: US CA Los Gatos
- Agency: Baker Botts L.L.P.
- Main IPC: H01L29/02
- IPC: H01L29/02 ; H01L21/336 ; H01L21/70

Abstract:
A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3′, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
Public/Granted literature
- US20140015067A1 SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS Public/Granted day:2014-01-16
Information query
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