A display device includes a display panel having pixels and divided into first and second display regions; first and second image interpolation chips which receive an original image signal and output interpolated ¼, ½, and/or ¾ frames inserted between a previous (n−1)-th frame and a current n-th frame of the original image signal; a first timing unit which receives the interpolated ¼, ½, and/or ¾ frames from the first image interpolation chip and outputs a first quadruple-speed image signal to pixels in the first display region; and a second timing unit which receives the interpolated ¼, ½, and/or ¾ frames from the second image interpolation chip and outputs a second quadruple-speed image signal to pixels in the second display region. The first timing unit transmits data to the second timing unit, and the second timing unit transmits data to the first timing unit.