Invention Grant
US08687411B2 Memory device, semiconductor device, and detecting method for defective memory cell in memory device
失效
存储器件,半导体器件和存储器件中的缺陷存储器单元的检测方法
- Patent Title: Memory device, semiconductor device, and detecting method for defective memory cell in memory device
- Patent Title (中): 存储器件,半导体器件和存储器件中的缺陷存储器单元的检测方法
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Application No.: US13344652Application Date: 2012-01-06
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Publication No.: US08687411B2Publication Date: 2014-04-01
- Inventor: Toshihiko Saito
- Applicant: Toshihiko Saito
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2011-005710 20110114
- Main IPC: G11C11/24
- IPC: G11C11/24

Abstract:
To provide a memory device which can perform verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, accurately in a short time. Each memory cell includes at least a first capacitor, a second capacitor, and a transistor which functions as a switching element for controlling supply, storage, and release of charge in the first capacitor and the second capacitor. The capacitance of the first capacitor is thousand or more times the capacitance of the second capacitor, preferably ten thousand or more times the capacitance of the second capacitor. In normal operation, charge is stored using the first capacitor and the second capacitor. In performing verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, charge is stored using the second capacitor.
Public/Granted literature
- US20120182789A1 MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND DETECTING METHOD Public/Granted day:2012-07-19
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