Invention Grant
US08688911B1 Transparent processing core and L2 cache connection 失效
透明处理核心和二级缓存连接

Transparent processing core and L2 cache connection
Abstract:
Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling the processing core to the BIU, the bridge module configured to selectively route information from the core bus agent to a cache or to the BIU by bypassing the cache. Other embodiments are also described and claimed.
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