Invention Grant
- Patent Title: Transparent processing core and L2 cache connection
- Patent Title (中): 透明处理核心和二级缓存连接
-
Application No.: US12624213Application Date: 2009-11-23
-
Publication No.: US08688911B1Publication Date: 2014-04-01
- Inventor: Tarek Rohana , Gil Stoler
- Applicant: Tarek Rohana , Gil Stoler
- Applicant Address: IL Yokneam
- Assignee: Marvell Israel (M.I.S.L) Ltd.
- Current Assignee: Marvell Israel (M.I.S.L) Ltd.
- Current Assignee Address: IL Yokneam
- Main IPC: G06F13/00
- IPC: G06F13/00

Abstract:
Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling the processing core to the BIU, the bridge module configured to selectively route information from the core bus agent to a cache or to the BIU by bypassing the cache. Other embodiments are also described and claimed.
Information query