In the embodiments, a full resistive network is used to determine resistance contributions to the total parasitic resistance of each source/drain region of a multi-fin multi-gate field effect transistor (MUGFET). These resistance contributions include: a first resistance contribution of end portions of the fins, which are connected in pseudo-parallel by a local interconnect; second resistance contributions of segments of the local interconnect, which are connected in pseudo-series; and any other resistance contributions of any other resistive elements between the end portions of the fins and a single resistive element through which all the diffusion region current flows. The multi-fin MUGFET is then represented in a netlist as a simple field effect transistor with the total parasitic resistances represented as single resistive elements connected to the source/drain nodes of that field effect transistor. This simplified netlist is then used to simulate performance of the multi-fin MUGFET.