Invention Grant
- Patent Title: Method for manufacturing a semiconductor device including application of a plating voltage
- Patent Title (中): 包括施加电镀电压的半导体装置的制造方法
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Application No.: US13548088Application Date: 2012-07-12
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Publication No.: US08691597B2Publication Date: 2014-04-08
- Inventor: Taku Kanaoka
- Applicant: Taku Kanaoka
- Applicant Address: JP Kawasaki-Shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2011-215188 20110929
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
An automatic analyzer detects voltage applied across electrodes, and judges whether voltage value falls within set voltage range. When the detected voltage value is lower than minimum value of set voltage range, the analyzer calculates the deficient amount of base solution based on the detected voltage value, controls a valve to supply the deficient amount of base solution, then, performs operation control of the valve so as to keep the prescribed amount of plating solution in plating solution tank, and discharges plating solution. When the detected voltage value is higher than maximum value of set voltage range, the analyzer calculates the excess amount of base solution based on the detected voltage value, controls a valve, and supplies pure water into the tank so that the base solution concentration falls within prescribed range to dilute plating solution, then controls a valve, and discharges plating solution so as to keep prescribed amount.
Public/Granted literature
- US20130084656A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE Public/Granted day:2013-04-04
Information query
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