Invention Grant
US08691644B2 Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor
有权
用应力通道NMOS晶体管和应变通道PMOS晶体管形成CMOS器件的方法
- Patent Title: Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor
- Patent Title (中): 用应力通道NMOS晶体管和应变通道PMOS晶体管形成CMOS器件的方法
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Application No.: US13541957Application Date: 2012-07-05
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Publication No.: US08691644B2Publication Date: 2014-04-08
- Inventor: Seung-Chul Song , Amitabh Jain , Deborah J. Riley
- Applicant: Seung-Chul Song , Amitabh Jain , Deborah J. Riley
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/336 ; H01L21/3205 ; H01L21/4763 ; H01L21/8234
Abstract:
A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.
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