Invention Grant
- Patent Title: Semiconductor device
- Patent Title (中): 半导体器件
-
Application No.: US13421010Application Date: 2012-03-15
-
Publication No.: US08692336B2Publication Date: 2014-04-08
- Inventor: Masaki Tamaru , Kazuyuki Nakanishi , Hidetoshi Nishimura
- Applicant: Masaki Tamaru , Kazuyuki Nakanishi , Hidetoshi Nishimura
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Panasonic Patent Center
- Priority: JP2009-294231 20091225
- Main IPC: H01L27/088
- IPC: H01L27/088

Abstract:
A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
Public/Granted literature
- US20120168875A1 SEMICONDUCTOR DEVICE Public/Granted day:2012-07-05
Information query
IPC分类: