Integrated circuits and methods for reducing the Single Event Upset (SEU) susceptibility of a memory cell are disclosed. By using one or more Through Silicon Vias (TSVs) as capacitor(s) coupled to the Q and/or Qbar nodes of the memory cell, the critical charge (Qcrit) of the circuit is increased. In so doing, the memory cell has greater resistance to an SEU occurrence and reduced sensitivity to neutron and alpha or other charged particle events. The capacitor(s) can be coupled between the Q or Qbar node(s) and a silicon substrate, or between the Q and Qbar nodes, for example.