Invention Grant
- Patent Title: Integrated circuit package system with waferscale spacer
- Patent Title (中): 集成电路封装系统，带有硅片间隔器
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Application No.: US13536268Application Date: 2012-06-28
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Publication No.: US08692388B2Publication Date: 2014-04-08
- Inventor: Sang-Ho Lee , Jong-Woo Ha , Soo-San Park
- Applicant: Sang-Ho Lee , Jong-Woo Ha , Soo-San Park
- Applicant Address: SG Singapore
- Assignee: Stats Chippac Ltd.
- Current Assignee: Stats Chippac Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
An integrated circuit packaging system is provided including: a first device having a first backside and a first active side; and a waferscale spacer having an exact fit at all four corners adjacent to an edge of the first device and a recess along the edge of the first device.
Public/Granted literature
- US20120261810A1 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WAFERSCALE SPACER Public/Granted day:2012-10-18
Information query
IPC分类:
