Invention Grant
- Patent Title: Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality
- Patent Title (中): 数字存储元件架构包括集成的2对1复用器功能
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Application No.: US11172534Application Date: 2005-06-30
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Publication No.: US08692592B2Publication Date: 2014-04-08
- Inventor: Charles M. Branch , Steven C. Bartling , Dharin N. Shah
- Applicant: Charles M. Branch , Steven C. Bartling , Dharin N. Shah
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03K21/00
- IPC: H03K21/00

Abstract:
A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.
Public/Granted literature
- US20070001733A1 Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality Public/Granted day:2007-01-04
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