Invention Grant
US08694736B2 Satisfying memory ordering requirements between partial reads and non-snoop accesses
有权
满足部分读取和非窥探访问之间的内存排序要求
- Patent Title: Satisfying memory ordering requirements between partial reads and non-snoop accesses
- Patent Title (中): 满足部分读取和非窥探访问之间的内存排序要求
-
Application No.: US13591157Application Date: 2012-08-21
-
Publication No.: US08694736B2Publication Date: 2014-04-08
- Inventor: Robert H. Beers , Ching-Tsun Chou , Robert J. Safranek , James Vash
- Applicant: Robert H. Beers , Ching-Tsun Chou , Robert J. Safranek , James Vash
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Caven & Aghevli LLC
- Main IPC: G06F13/18
- IPC: G06F13/18

Abstract:
A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.
Public/Granted literature
- US20120317369A1 SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND NON-SNOOP ACCESSES Public/Granted day:2012-12-13
Information query